01 / GaN
The speed layer
Model n-GaN HEMTs and experimental p-GaN/AlN 2DHG devices for fast switching, logic and low-precision AI arithmetic.
- Fast switching and local compute
- Low-precision AI research paths
- Scalable tile-level exploration
+ Wide-bandgap AI compute
Rethinking AI hardware beyond silicon CMOS
AURORA-X explores whether GaN speed layers and SiC control and power layers can form a new architecture for energy-efficient AI compute.
Simulation platformv0.3.1Pre-silicon research
01GaNSpeed layer
02SiCControl + power
RESEARCH NOTE01
Research premise
Speed where computation happens. Strength where power is controlled.
02 / SiC
The strength layer
Model SiC JFET devices as power-domain controllers and support elements where breakdown strength and thermal resilience matter.
- Power-domain control
- Power gating and wake analysis
- Thermal and idle-leakage trade-offs
ARCHITECTURE STUDY02
Candidate architectures
Five paths. One evidence-driven decision framework.
The simulator scores each candidate across energy, thermal behavior, p-GaN feasibility, voltage compatibility, interface overhead, scalability, research difficulty and clarity of the engineering case.
GaN-first compute tile
A baseline path focused on fast switching and local AI arithmetic.
↗SiC-managed power tile
Separates fast compute activity from resilient power-domain control.
↗Cross-domain support tile
Studies the cost of communication between distinct device domains.
↗Power-gated hybrid tile
Explores idle-energy savings against wake-up and control overhead.
↗Dynamic hybrid logic tile
Tests alternative logic styles that could reduce dependence on difficult complementary devices.
↗SIMULATION PLATFORM03
From device to transformer
A simulator built to expose blockers—not hide them.
AURORA-X connects device assumptions to circuit behavior, tile performance, thermal limits and transformer workload estimates. Every version narrows the gap between a promising idea and a testable research plan.
01
Devices
GaN HEMT · p-GaN · SiC JFET
02
Circuits
Logic · latch · register file
03
Compute
MAC · FP8 assist · tiles
04
Systems
Thermal · joules per token
31baseline tests passing
5architecture candidates
8decision dimensions
6logic relaxation modes
PUBLIC RESEARCH FINDINGS04
What the simulator has taught us
Promising materials do not automatically create a viable architecture.
These are qualitative, simulation-led observations. Exact thresholds, proprietary configurations and unpublished implementation details are intentionally excluded pending external validation and IP review.
Complementary device feasibility is a first-order constraint
The modeled architecture is highly sensitive to the maturity and balance of p-type wide-bandgap devices. This remains a research question, not a solved assumption.
Interfaces can erase device-level gains
Energy and delay introduced between GaN compute and SiC control domains must be evaluated as part of the architecture—not treated as a negligible adapter cost.
Hybrid logic reduces one burden by creating another
Dynamic and power-managed approaches may reduce dependence on complementary GaN, but they introduce control, wake-up and verification complexity.
Power gating has a measurable break-even point
Idle savings are meaningful only when the idle period and tile scale justify the wake energy and delay. The simulator treats this as a search problem rather than a universal benefit.
RESEARCH STATUS05
Current evidence level
Pre-silicon, simulation-led and explicitly falsifiable.
Simulation evidence
Architecture hypotheses and modeled trade-offs—not fabricated-chip measurements.
AURORA-X is an exploratory research platform. Its outputs depend on device-model assumptions and require calibration against published measurements, TCAD/SPICE data and eventually physical prototypes.
This distinction is central to the project: promising candidates are treated as research directions, not performance claims.
PUBLIC DISCLOSURE BOUNDARY
Detailed device parameters, raw simulator outputs, circuit schematics, optimization thresholds, source code and proof-cell implementation details are retained for controlled technical and IP review.
PROJECT PROGRESS06
Completed · active · next
A clear boundary between what exists today and what still needs proof.
01
Completed
- Device-to-workload simulation baseline
- Logic, arithmetic and AI-tile models
- Alternative architecture exploration
- Voltage-domain and interface analysis
- Break-even and blocker search
- Five-candidate decision framework
02
In progress
- Calibration against published measurements
- Confidence ranges for device assumptions
- Cross-domain interface feasibility
- Selection of a demonstrator circuit
03
Next
- Independent university review
- Higher-fidelity SPICE or TCAD validation
- Small experimental proof point
- Publication and IP review before deeper disclosure
DEVELOPMENT LOG07
Research roadmap
Each release turns uncertainty into a measurable engineering target.
Completed
Device-to-workload baseline
31 tests covering GaN and SiC devices, logic, arithmetic, tiles, thermal behavior and transformer decode estimation.
Completed
Threshold search
Heatmaps, binary search and coordinate descent identify minimum device improvements and circuit bottlenecks.
Completed
Joint feasibility envelope
Optimization, voltage-domain interfaces and break-even analysis test alternative logic and control strategies.
Completed
Architecture decision engine
Five candidates are ranked across energy, thermal, device feasibility, interfaces, scalability and research difficulty.
Current release
Failure-to-pass roadmap
For every failing candidate, the simulator estimates the smallest parameter changes required to reach a pass condition.
PARTNERSHIP PATHWAYS08
Research · investment
Different partners. One shared goal: turn a testable hypothesis into evidence.
AURORA-X is looking for technically rigorous collaboration—not endorsements. Every partnership should move the project toward better models, independent validation or a focused experimental proof point.
Research collaboration
Relevant areas include p-type wide-bandgap devices, complementary logic, cross-domain circuits, thermal modeling and device-model calibration.
- Independent technical review
- SPICE or TCAD model validation
- Joint proof-cell definition
- Publication pathways after IP review
Investment and strategic support
The immediate opportunity is to fund validation milestones, expert collaboration and a small experimental demonstrator—not to claim a production-ready chip.
- Milestone-based research support
- Semiconductor ecosystem access
- University and laboratory introductions
- IP and commercialization guidance
RESEARCH FAQ09
Frequently asked
What AURORA-X is—and what it is not.
What is AURORA-X?
AURORA-X is an independent pre-silicon research and simulation project exploring whether GaN and SiC devices can support a new energy-efficient AI-compute architecture.
Has an AURORA-X chip been fabricated?
No. The current evidence is simulation-led. The next objective is external model validation followed by a deliberately small experimental proof point.
Why combine GaN and SiC?
The research hypothesis assigns fast switching and selected compute roles to GaN, while SiC is studied for control, power-domain management and thermal resilience. Interface overhead remains a central uncertainty.
What collaboration is AURORA-X seeking?
The project is seeking university researchers, device physicists, circuit designers, semiconductor laboratories and deep-tech partners who can strengthen validation and experimental planning.
Open research collaboration
Help move AURORA-X from simulation toward experimental validation.
We are seeking university researchers, semiconductor device experts, circuit designers and early-stage deep-tech partners.